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74HC595 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
High-Performance Silicon-Gate CMOS
The 74HC595 consists of an 8-bit shift register and an 8-bit D-type latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595 directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.
Features http://onsemi.com MARKING DIAGRAMS
16 16 1 SOIC-16 D SUFFIX CASE 751B 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 HC 595 ALYW G G HC595G AWLYWW
* * * * * * * * *
*
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595 - Improved Propagation Delays - 50% Lower Quiescent Power - Improved Input Noise and Latchup Immunity These are Pb-Free Devices
HC595 = Device Code A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
March, 2007 - Rev. 1
1
Publication Order Number: 74HC595/D
74HC595
LOGIC DIAGRAM
SERIAL DATA INPUT A 14 15 1 2 3 SHIFT REGISTER 4 LATCH 5 6 7 SHIFT 11 CLOCK 10 RESET LATCH 12 CLOCK OUTPUT 13 ENABLE QA QB QC QD QE QF QG QH PARALLEL DATA OUTPUTS
PIN ASSIGNMENT
QB QC QD QE QF QG QH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC QA A OUTPUT ENABLE LATCH CLOCK SHIFT CLOCK RESET SQH
9
SQH
SERIAL DATA OUTPUT
VCC = PIN 16 GND = PIN 8
ORDERING INFORMATION
Device 74HC595DR2G 74HC595DTR2G Package SOIC-16 (Pb-Free) TSSOP-16* Shipping 2500 Tape & Reel 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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74HC595
IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS
Symbol VCC Vin Iin Iout ICC PD Tstg TL Vout Parameter Value Unit V V V mA mA mA mW _C _C DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 500 450 - 65 to + 150 260 DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (SOIC or TSSOP Package) SOIC Package TSSOP Package
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vin, Vout TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min 2.0 0 - 55 0 0 0 Max 6.0 VCC + 125 1000 500 400 Unit V V _C ns
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74HC595
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA IIoutI v 4.0 mA IIoutIv 5.2 mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA IIoutI v 4.0 mA IIoutIv 5.2 mA 3.0 4.5 6.0 6.0 6.0 Guaranteed Limit - 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 1.9 4.4 5.9 2.98 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 0.1 0.25 v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 1.0 2.5 v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 1.0 2.5 mA mA V V V Unit V
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage, QA - QH
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
V
VOL
Maximum Low-Level Output Voltage, QA - QH
Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL
VOH
Minimum High-Level Output Voltage, SQH
Vin = VIH or VIL IIoutI v 20 mA Vin = VIH or VIL
VOL
Maximum Low-Level Output Voltage, SQH
Vin = VIH or VIL IIoutI v 20 mA Vin = VIH or VIL
Iin IOZ
Maximum Input Leakage Current Maximum Three-State Leakage Current, QA - QH Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND lout = 0 mA
ICC
6.0
4.0
40
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC595
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 7) VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - - Guaranteed Limit - 55 to 25_C 6.0 15 30 35 140 100 28 24 145 100 29 25 140 100 28 24 150 100 30 26 135 90 27 23 60 23 12 10 75 27 15 13 10 15 v 85_C 4.8 10 24 28 175 125 35 30 180 125 36 31 175 125 35 30 190 125 38 33 170 110 34 29 75 27 15 13 95 32 19 16 10 15 v 125_C 4.0 8.0 20 24 210 150 42 36 220 150 44 38 210 150 42 36 225 150 45 38 205 130 41 35 90 31 18 15 110 36 22 19 10 15 Unit MHz
tPLH, tPHL
Maximum Propagation Delay, Shift Clock to SQH (Figures 1 and 7)
ns
tPHL
Maximum Propagation Delay, Reset to SQH (Figures 2 and 7)
ns
tPLH, tPHL
Maximum Propagation Delay, Latch Clock to QA - QH (Figures 3 and 7)
ns
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to QA - QH (Figures 4 and 8)
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to QA - QH (Figures 4 and 8)
ns
tTLH, tTHL
Maximum Output Transition Time, QA - QH (Figures 3 and 7)
ns
tTLH, tTHL
Maximum Output Transition Time, SQH (Figures 1 and 7)
ns
Cin Cout
Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High-Impedance State), QA - QH
pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 300 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC595
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Symbol tsu Parameter Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5) VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 Guaranteed Limit 25_C to -55_C 50 40 10 9.0 75 60 15 13 5.0 5.0 5.0 5.0 50 40 10 9.0 60 45 12 10 50 40 10 9.0 50 40 10 9.0 1000 800 500 400 v 85_C 65 50 13 11 95 70 19 16 5.0 5.0 5.0 5.0 65 50 13 11 75 60 15 13 65 50 13 11 65 50 13 11 1000 800 500 400 v 125_C 75 60 15 13 110 80 22 19 5.0 5.0 5.0 5.0 75 60 15 13 90 70 18 15 75 60 15 13 75 60 15 13 1000 800 500 400 Unit ns
tsu
Minimum Setup Time, Shift Clock to Latch Clock (Figure 6)
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5)
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2)
ns
tw
Minimum Pulse Width, Reset (Figure 2)
ns
tw
Minimum Pulse Width, Shift Clock (Figure 1)
ns
tw
Minimum Pulse Width, Latch Clock (Figure 6)
ns
tr, tf
Maximum Input Rise and Fall Times (Figure 1)
ns
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74HC595
FUNCTION TABLE
Inputs Serial Input A X D X X Shift Clock X L, H, L, H, Latch Clock L, H, L, H, L, H, Output Enable L L L L Shift Register Contents L DSRA; SRNSRN+1 U U Resulting Function Latch Register Contents U U U SRNLRN Serial Output SQH L SRGSRH U U Parallel Outputs QA - QH U U U SRN
Operation Reset shift register Shift data into shift register Shift register remains unchanged Transfer shift register contents to latch register Latch register remains unchanged Enable parallel outputs Force outputs into high impedance state
Reset L H H H
X X X
X X X
X X X
L, H, X X
L L H = Low-to-High = High-to-Low
* * *
U ** **
* * *
U Enabled Z
SR = shift register contents LR = latch register contents
D = data (L, H) logic level U = remains unchanged
* = depends on Reset and Shift Clock inputs ** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS A (Pin 14) Output Enable (Pin 13)
Serial Data Input. The data on this pin is shifted into the 8-bit serial shift register.
CONTROL INPUTS Shift Clock (Pin 11)
Active-low Output Enable. A low on this input allows the data from the latches to be presented at the outputs. A high on this input forces the outputs (QA-QH) into the high-impedance state. The serial output is not affected by this control unit.
OUTPUTS QA - QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Shift Register Clock Input. A low- to-high transition on this input causes the data at the Serial Input pin to be shifted into the 8-bit shift register.
Reset (Pin 10)
Noninverted, 3-state, latch outputs.
SQH (Pin 9)
Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift register portion of this device only. The 8-bit latch is not affected.
Latch Clock (Pin 12)
Noninverted, Serial Data Output. This is the output of the eighth stage of the 8-bit shift register. This output does not have three-state capability.
Storage Latch Clock Input. A low-to-high transition on this input latches the shift register data.
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74HC595
SWITCHING WAVEFORMS
tr SHIFT CLOCK 90% 50% 10% tw 1/fmax tPLH OUTPUT SQH 90% 50% 10% tTLH tTHL tPHL tf VCC GND OUTPUT SQH SHIFT CLOCK RESET tPHL 50% trec 50% VCC GND 50% tw VCC GND
Figure 1.
VCC GND tPLH 90% QA-QH 50% OUTPUTS 10% tTLH tTHL tPHL OUTPUT ENABLE 50%
Figure 2.
VCC tPZL 50% tPZH OUTPUT Q 50% tPHZ tPLZ 10% 90% GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
LATCH CLOCK
50%
OUTPUT Q
Figure 3.
SHIFT CLOCK
Figure 4.
VCC GND tsu LATCH CLOCK 50% tw VCC GND
VALID SERIAL INPUT A SWITCH CLOCK 50% tsu th 50%
VCC GND VCC GND
50%
Figure 5.
Figure 6.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7.
Figure 8.
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74HC595
EXPANDED LOGIC DIAGRAM
OUTPUT ENABLE LATCH CLOCK SERIAL DATA INPUT A 13
12
14
D SRA R D SRB R D SRC R D SRD R D SRE R D SRF R D SRG R D SRH R
Q
D LRA
Q
15
QA
Q
D LRB
Q
1
QB
Q
D LRC
Q
2
QC
Q
D LRD
Q
3
QD PARALLEL DATA OUTPUTS
Q
D LRE
Q
4
QE
Q
D LRF
Q
5
QF
Q
D LRG
Q
6
QG
SHIFT CLOCK
Q
D LRH
Q
7
11
QH
RESET
10
9
SERIAL DATA OUTPUT SQH
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74HC595
TIMING DIAGRAM
SHIFT CLOCK SERIAL DATA INPUT A RESET LATCH CLOCK OUTPUT ENABLE QA QB QC QD QE QF QG QH SERIAL DATA OUTPUT SQH NOTE: implies that the output is in a high-impedance state.
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74HC595
PACKAGE DIMENSIONS
SOIC-16 CASE 751B-05 ISSUE K
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
SOLDERING FOOTPRINT*
6.40
16X 8X
1.12 16
1
16X
0.58
1.27 PITCH 8 9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC595
PACKAGE DIMENSIONS
TSSOP-16 CASE 948F-01 ISSUE B
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
2X
L/2
16
9
J1 B -U-
SECTION N-N J N
L
PIN 1 IDENT. 1 8
0.15 (0.006) T U
S
A -V-
N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
16X
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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CCC EEE CCC EEE CCC
0.25 (0.010) M
K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC595
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PUBLICATION ORDERING INFORMATION
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74HC595/D

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